Transmission line interconnect structures are employed in multiple IC applications. However, their characteristics (delay and characteristic impedance) are fixed once they are fabricated. In many situations, to modify the characteristics of such interconnects it is desirable to make the IC reconfigurable, to compensate for process variations, or to make fine adjustments and improve performance.
A problem with the present solutions is that the configurability depends on FET switches fabricated in the front end of the line (FEOL) or other conventional FEOL switches or devices such as BJTs, HBTs, diodes, etc. The parasitics associated with such switches and devices (including vias to descend to the FEOL) are difficult to model, they decrease tunability and increase loss.